The phase locked loop (PLL) is a common method of frequency synthesis in modern communications. Among other uses, conventional PLLs are integral components in wireless communication transceivers and are also used for FM and AM modulation and demodulation, data and tape synchronization, frequency shift keying, tone decoding, frequency multiplication and division, signal regeneration, and control mechanisms in robotics, radio and satellite. A PLL normally includes a phase-frequency detector (PFD), a PLL charge pump and a voltage controlled oscillator (VCO). It is understood that another resonator element or any frequency generating element can replace a VCO in such a PLL. A PLL can also include a divider, loop filter, or a number of other devices depending on the intended output frequency of the PLL.
The PLL is normally configured to receive a reference frequency signal and transmit a desired output frequency signal. Specifically, in a conventional PLL, the reference frequency is coupled to a PFD. The PFD is coupled to a VCO. PFD is configured to receive the reference frequency and also the output frequency generated by the VCO. The PFD is also coupled to the PLL charge pump. The PFD detector transmits, and the PLL charge pump is configured to receive, an error signal with a value based on a phase and/or frequency difference between the reference frequency and the output frequency. The error signal causes the PLL charge pump to change its control voltage which adjusts the oscillation frequency of the VCO until the phase of the output frequency matches the phase of the reference frequency. This feedback loop causes the output frequency to phase lock on the reference frequency.
If a higher or lower output frequency is desired, a frequency divider or multiplier can be introduced between the output frequency of the VCO and the phase detector to manipulate the frequency to be smaller or larger. To simplify this discussion, only a divider will be considered though a multiplier can be substituted for the divider. A divider can be configured to receive the output frequency and transmit a manipulated frequency to the phase detector based on the value of the divider. The PFD generates a voltage control signal to the VCO in response to differences between the reference frequency and the manipulated frequency. The voltage control signal is provided until the phase of the reference frequency matches the phase of the manipulated frequency. The PLL thereby locks its phase to a fraction or multiple of the reference frequency. Thus, a variety of frequencies can be produced from a single reference frequency by changing the value of the divider.
In integrated circuit transceivers, the VCO must be designed to operate over the desired frequency range plus an extra allowance for process and temperature variations. This extra allowance may expand the frequency range up to three to four times the actual desired frequency range. This action requires an increase the in VCO gain (KVCO). This is contrary to high-performance transceiver design because it results in a frequency synthesizer with unacceptably large phase noise. A possible solution to the problem is to implement the PLL using several lower gain VCOs that together span the total frequency range including allowances for process and temperature variations. Multiple VCOs could be realized as physically separate circuits, a single oscillator with switchable resonator elements, or a combination of both. However, this solution creates a new problem of selecting the proper VCO and/or a configuration of switchable resonator elements to produce the desired frequency.
This has been approached several different ways. One early method describes a PLL with multiple loop filters and VCOs designed to synthesize frequencies over a broad range, perhaps several decades of frequencies. The proper VCO is selected by using a window comparator on the currently selected VCO's tuning voltage. Because a PFD is used, if the tuning voltage is in the window, the PLL locks.
A later solution prescribes the circuit to select the proper VCO using a lock detection circuit and sequentially trying each VCO until one of them locks. The lock detector could be implemented by a window comparator or as a digital circuit.
However, neither of these solutions find the optimal VCO, but simply the first one that locks. For example, two VCOs can lock and either can be chosen randomly or by predetermined means. Another scheme attempts find the optimum VCO by producing a table of the lock/unlock status for each of the VCOs. If multiple VCOs lock, the VCO in the middle is selected. Although the algorithm could terminate in as little as two iterations, as many as M iterations can be required for the algorithm to succeed, where M is the total number of VCOs. Having a variable number of iterations, and therefore a variable time required to select the optimum VCO is a disadvantage because the design of the system in which the PLL is used must be made assuming the worst case, or most time consuming condition.
Another solution describes how to select the optimum VCO when using multiple VCOs within the desired range of frequencies. A binary search is used to determine the optimal crossover frequency between each pair of VCOs. This solution leaves an unsolved problem of selecting a frequency range in which the optimum VCO is, which requires more circuitry.
Another example uses a frequency synthesizer including a calibration circuit, where that calibration circuit requires fixing the VCO input to a specific voltage and a separate frequency comparator computes the difference between the reference frequency and a prescaled VCO output frequency. A binary search is then used to select the proper VCO. However, additional circuitry is required for the frequency comparison. Furthermore, because the VCO input voltage must be switched, extra circuitry must be placed on the tuning voltage signal which results in increased phase noise. At the multiple gigahertz frequencies at which modern wireless appliances operate at, this noise is unacceptable. Each of these prior attempts has one or more difficulties. A simplified and improved approach is needed.